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idp.hpp File Reference

Detailed Description

Contains definition of the interface to IDP modules.

The interface consists of 2 structures:

These structures contain information about processor features, function pointers, etc.


struct  bytes_t
 Structure used to describe byte streams (for "ret" instruction and empirics) More...
struct  instruc_t
 Internal representation of processor instructions. More...
struct  asm_t
 Describes the target assembler. More...
struct  processor_t
 Describes a processor module (IDP). More...
struct  reg_info_t
 Get register number and size from register name. More...


bool has_cf_chg (uint32 feature, uint opnum)
 Does an instruction with the specified feature modify the i-th operand?
bool has_cf_use (uint32 feature, uint opnum)
 Does an instruction with the specified feature use a value of the i-th operand?
idaman bool ida_export has_insn_feature (int icode, uint32 bit)
 Does the specified instruction have the specified feature?
idaman bool ida_export is_call_insn (const insn_t &insn)
 Is the instruction a "call"?
idaman bool ida_export is_ret_insn (const insn_t &insn, bool strict=true)
 Is the instruction a "return"?
idaman bool ida_export is_indirect_jump_insn (const insn_t &insn)
 Is the instruction an indirect jump?
idaman bool ida_export is_basic_block_end (const insn_t &insn, bool call_insn_stops_block)
 Is the instruction the end of a basic block?
 CASSERT (sizeof(processor_t)==104)
idaman int ida_export str2reg (const char *p)
 Get any reg number (-1 on error)
idaman int ida_export is_align_insn (ea_t ea)
 If the instruction at 'ea' looks like an alignment instruction, return its length in bytes. More...
idaman ssize_t ida_export get_reg_name (qstring *buf, int reg, size_t width, int reghi=-1)
 Get text representation of a register. More...
const char * get_reg_info (const char *regname, bitrange_t *bitrange)
 Get register information - useful for registers like al, ah, dil, etc. More...
idaman bool ida_export parse_reg_name (reg_info_t *ri, const char *regname)
 Get register info by name. More...
size_t sizeof_ldbl (void)
 Get size of long double.
idaman bool ida_export set_processor_type (const char *procname, setproc_level_t level)
 Set target processor type. More...
idaman char *ida_export get_idp_name (char *buf, size_t bufsize)
 Get name of the current processor module. More...
idaman bool ida_export set_target_assembler (int asmnum)
 Set target assembler. More...
bool delay_slot_insn (ea_t *ea, bool *bexec, bool *fexec)
 Helper function to get the delay slot instruction.


 IDB event group.


 The interface version number. More...
#define CF_STOP   0x00001
 Instruction doesn't pass execution to the. More...
#define CF_CALL   0x00002
 CALL instruction (should make a procedure here)
#define CF_CHG1   0x00004
 The instruction modifies the first operand.
#define CF_CHG2   0x00008
 The instruction modifies the second operand.
#define CF_CHG3   0x00010
 The instruction modifies the third operand.
#define CF_CHG4   0x00020
 The instruction modifies 4 operand.
#define CF_CHG5   0x00040
 The instruction modifies 5 operand.
#define CF_CHG6   0x00080
 The instruction modifies 6 operand.
#define CF_USE1   0x00100
 The instruction uses value of the first operand.
#define CF_USE2   0x00200
 The instruction uses value of the second operand.
#define CF_USE3   0x00400
 The instruction uses value of the third operand.
#define CF_USE4   0x00800
 The instruction uses value of the 4 operand.
#define CF_USE5   0x01000
 The instruction uses value of the 5 operand.
#define CF_USE6   0x02000
 The instruction uses value of the 6 operand.
#define CF_JUMP   0x04000
 The instruction passes execution using indirect. More...
#define CF_SHFT   0x08000
 Bit-shift instruction (shl,shr...)
#define CF_HLL   0x10000
 Instruction may be present in a high level. More...
#define CF_CHG7   0x020000
 The instruction modifies the 7th operand.
#define CF_CHG8   0x040000
 The instruction modifies the 8th operand.
#define CF_USE7   0x080000
 The instruction uses value of the 7th operand.
#define CF_USE8   0x100000
 The instruction uses value of the 8th operand.
#define AS_OFFST   0x00000001L
 offsets are 'offset xxx' ?
#define AS_COLON   0x00000002L
 create colons after data names ?
#define AS_UDATA   0x00000004L
 can use '?' in data directives
#define AS_2CHRE   0x00000008L
 double char constants are: "xy
#define AS_NCHRE   0x00000010L
 char constants are: 'x
#define AS_N2CHR   0x00000020L
 can't have 2 byte char consts
#define AS_1TEXT   0x00000040L
 1 text per line, no bytes
#define AS_NHIAS   0x00000080L
 no characters with high bit
#define AS_NCMAS   0x00000100L
 no commas in ascii directives
#define AS_HEXFM   0x00000E00L
 mask - hex number format
#define ASH_HEXF0   0x00000000L
#define ASH_HEXF1   0x00000200L
#define ASH_HEXF2   0x00000400L
#define ASH_HEXF3   0x00000600L
#define ASH_HEXF4   0x00000800L
#define ASH_HEXF5   0x00000A00L
 <^R > (radix)
#define AS_DECFM   0x00003000L
 mask - decimal number format
#define ASD_DECF0   0x00000000L
#define ASD_DECF1   0x00001000L
#define ASD_DECF2   0x00002000L
#define ASD_DECF3   0x00003000L
#define AS_OCTFM   0x0001C000L
 mask - octal number format
#define ASO_OCTF0   0x00000000L
#define ASO_OCTF1   0x00004000L
#define ASO_OCTF2   0x00008000L
#define ASO_OCTF3   0x0000C000L
#define ASO_OCTF4   0x00010000L
#define ASO_OCTF5   0x00014000L
#define ASO_OCTF6   0x00018000L
#define ASO_OCTF7   0x0001C000L
#define AS_BINFM   0x000E0000L
 mask - binary number format
#define ASB_BINF0   0x00000000L
#define ASB_BINF1   0x00020000L
#define ASB_BINF2   0x00040000L
#define ASB_BINF3   0x00060000L
#define ASB_BINF4   0x00080000L
#define ASB_BINF5   0x000A0000L
#define AS_UNEQU   0x00100000L
 replace undefined data items with EQU (for ANTA's A80)
#define AS_ONEDUP   0x00200000L
 One array definition per line.
#define AS_NOXRF   0x00400000L
 Disable xrefs during the output file generation.
#define AS_XTRNTYPE   0x00800000L
 Assembler understands type of extern symbols as ":type" suffix.
#define AS_RELSUP   0x01000000L
 Checkarg: 'and','or','xor' operations with addresses are possible.
#define AS_LALIGN   0x02000000L
 Labels at "align" keyword are supported.
#define AS_NOCODECLN   0x04000000L
 don't create colons after code names
#define AS_NOSPACE   0x10000000L
 No spaces in expressions.
#define AS_ALIGN2   0x20000000L
 .align directive expects an exponent rather than a power of 2 More...
#define AS_ASCIIC   0x40000000L
 ascii directive accepts C-like escape sequences More...
#define AS_ASCIIZ   0x80000000L
 ascii directive inserts implicit zero byte at the end
#define AS2_BRACE   0x00000001
 Use braces for all expressions.
#define AS2_STRINV   0x00000002
 Invert meaning of idainfo::wide_high_byte_first for text strings. More...
#define AS2_BYTE1CHAR   0x00000004
 One symbol per processor byte. More...
#define AS2_IDEALDSCR   0x00000008
 Description of struc/union is in. More...
#define AS2_TERSESTR   0x00000010
 'terse' structure initialization form More...
#define AS2_COLONSUF   0x00000020
 addresses may have ":xx" suffix More...
#define AS2_YWORD   0x00000040
 a_yword field is present and valid
#define PLFM_386   0
 Intel 80x86.
#define PLFM_Z80   1
 8085, Z80
#define PLFM_I860   2
 Intel 860.
#define PLFM_8051   3
#define PLFM_TMS   4
 Texas Instruments TMS320C5x.
#define PLFM_6502   5
#define PLFM_PDP   6
#define PLFM_68K   7
 Motorola 680x0.
#define PLFM_JAVA   8
#define PLFM_6800   9
 Motorola 68xx.
#define PLFM_ST7   10
 SGS-Thomson ST7.
#define PLFM_MC6812   11
 Motorola 68HC12.
#define PLFM_MIPS   12
#define PLFM_ARM   13
 Advanced RISC Machines.
#define PLFM_TMSC6   14
 Texas Instruments TMS320C6x.
#define PLFM_PPC   15
#define PLFM_80196   16
 Intel 80196.
#define PLFM_Z8   17
#define PLFM_SH   18
 Renesas (formerly Hitachi) SuperH.
#define PLFM_NET   19
 Microsoft Visual Studio.Net.
#define PLFM_AVR   20
 Atmel 8-bit RISC processor(s)
#define PLFM_H8   21
 Hitachi H8/300, H8/2000.
#define PLFM_PIC   22
 Microchip's PIC.
#define PLFM_SPARC   23
#define PLFM_ALPHA   24
 DEC Alpha.
#define PLFM_HPPA   25
 Hewlett-Packard PA-RISC.
#define PLFM_H8500   26
 Hitachi H8/500.
#define PLFM_TRICORE   27
 Tasking Tricore.
#define PLFM_DSP56K   28
 Motorola DSP5600x.
#define PLFM_C166   29
 Siemens C166 family.
#define PLFM_ST20   30
 SGS-Thomson ST20.
#define PLFM_IA64   31
 Intel Itanium IA64.
#define PLFM_I960   32
 Intel 960.
#define PLFM_F2MC   33
 Fujistu F2MC-16.
#define PLFM_TMS320C54   34
 Texas Instruments TMS320C54xx.
#define PLFM_TMS320C55   35
 Texas Instruments TMS320C55xx.
#define PLFM_TRIMEDIA   36
#define PLFM_M32R   37
 Mitsubishi 32bit RISC.
#define PLFM_NEC_78K0   38
 NEC 78K0.
#define PLFM_NEC_78K0S   39
 NEC 78K0S.
#define PLFM_M740   40
 Mitsubishi 8bit.
#define PLFM_M7700   41
 Mitsubishi 16bit.
#define PLFM_ST9   42
#define PLFM_FR   43
 Fujitsu FR Family.
#define PLFM_MC6816   44
 Motorola 68HC16.
#define PLFM_M7900   45
 Mitsubishi 7900.
#define PLFM_TMS320C3   46
 Texas Instruments TMS320C3.
#define PLFM_KR1878   47
 Angstrem KR1878.
#define PLFM_AD218X   48
 Analog Devices ADSP 218X.
#define PLFM_OAKDSP   49
 Atmel OAK DSP.
#define PLFM_TLCS900   50
 Toshiba TLCS-900.
#define PLFM_C39   51
 Rockwell C39.
#define PLFM_CR16   52
 NSC CR16.
#define PLFM_MN102L00   53
 Panasonic MN10200.
#define PLFM_TMS320C1X   54
 Texas Instruments TMS320C1x.
#define PLFM_NEC_V850X   55
 NEC V850 and V850ES/E1/E2.
#define PLFM_SCR_ADPT   56
 Processor module adapter for processor modules written in scripting languages.
#define PLFM_EBC   57
 EFI Bytecode.
#define PLFM_MSP430   58
 Texas Instruments MSP430.
#define PLFM_SPU   59
 Cell Broadband Engine Synergistic Processor Unit.
#define PLFM_DALVIK   60
 Android Dalvik Virtual Machine.
#define PLFM_65C816   61
#define PLFM_M16C   62
 Renesas M16C.
#define PLFM_ARC   63
 Argonaut RISC Core.
#define PLFM_UNSP   64
 SunPlus unSP.
#define PLFM_TMS320C28   65
 Texas Instruments TMS320C28x.
#define PLFM_DSP96K   66
 Motorola DSP96000.
#define PLFM_SPC700   67
 Sony SPC700.
#define PLFM_AD2106X   68
 Analog Devices ADSP 2106X.
#define PR_SEGS   0x000001
 has segment registers?
#define PR_USE32   0x000002
 supports 32-bit addressing?
#define PR_DEFSEG32   0x000004
 segments are 32-bit by default
#define PR_RNAMESOK   0x000008
 allow user register names for location names
#define PR_ADJSEGS   0x000020
 IDA may adjust segments' starting/ending addresses.
#define PR_DEFNUM   0x0000C0
 mask - default number representation
#define PRN_HEX   0x000000
#define PRN_OCT   0x000040
#define PRN_DEC   0x000080
#define PRN_BIN   0x0000C0
#define PR_WORD_INS   0x000100
 instruction codes are grouped 2bytes in binary line prefix
#define PR_NOCHANGE   0x000200
 The user can't change segments and code/data attributes. More...
#define PR_ASSEMBLE   0x000400
 Module has a built-in assembler and will react to ev_assemble.
#define PR_ALIGN   0x000800
 All data items should be aligned properly.
#define PR_TYPEINFO   0x001000
 the processor module supports type information callbacks More...
#define PR_USE64   0x002000
 supports 64-bit addressing?
#define PR_SGROTHER   0x004000
 the segment registers don't contain the segment selectors.
#define PR_STACK_UP   0x008000
 the stack grows up
#define PR_BINMEM   0x010000
 the processor module provides correct segmentation for binary files More...
#define PR_SEGTRANS   0x020000
 the processor module supports the segment translation feature More...
#define PR_CHK_XREF   0x040000
 don't allow near xrefs between segments with different bases
#define PR_NO_SEGMOVE   0x080000
 the processor module doesn't support move_segm() More...
#define PR_USE_ARG_TYPES   0x200000
 use processor_t::use_arg_types callback
#define PR_SCALE_STKVARS   0x400000
 use processor_t::get_stkvar_scale callback
#define PR_DELAYED   0x800000
 has delayed jumps and calls More...
#define PR_ALIGN_INSN   0x1000000
 allow ida to create alignment instructions arbitrarily. More...
#define PR_PURGING   0x2000000
 there are calling conventions which may purge bytes from the stack
#define PR_CNDINSNS   0x4000000
 has conditional instructions
#define PR_USE_TBYTE   0x8000000
#define PR_DEFSEG64   0x10000000
 segments are 64-bit by default
#define PR_OUTER   0x20000000
 has outer operands (currently only mc68k)
#define PR2_MAPPINGS   0x000001
 the processor module uses memory mapping
#define PR2_IDP_OPTS   0x000002
 the module has processor-specific configuration options
#define PR2_REALCVT   0x000004
 the module has 'realcvt' event implementation
#define CUSTOM_INSN_ITYPE   0x8000
 Custom instruction codes defined by processor extension plugins must be greater than or equal to this.
#define REG_SPOIL   0x80000000L
 processor_t::use_regarg_type uses this bit in the return value to indicate that the register value has been spoiled
#define OP_FP_BASED   0x00000000
 operand is FP based
#define OP_SP_BASED   0x00000001
 operand is SP based
#define OP_SP_ADD   0x00000000
 operand value is added to the pointer
#define OP_SP_SUB   0x00000002
 operand value is subtracted from the pointer


typedef int help_t
 help screen number
typedef qvector< reg_info_treginfovec_t
 vector of register info objects


 Flags passed as 'level' parameter to set_processor_type() More...
enum  idb_event::event_code_t {
  idb_event::closebase, idb_event::savebase, idb_event::upgraded, idb_event::auto_empty,
  idb_event::auto_empty_finally, idb_event::determined_main, idb_event::local_types_changed, idb_event::extlang_changed,
  idb_event::idasgn_loaded, idb_event::kernel_config_loaded, idb_event::loader_finished, idb_event::flow_chart_created,
  idb_event::compiler_changed, idb_event::changing_ti, idb_event::ti_changed, idb_event::changing_op_ti,
  idb_event::op_ti_changed, idb_event::changing_op_type, idb_event::op_type_changed, idb_event::enum_created,
  idb_event::deleting_enum, idb_event::enum_deleted, idb_event::renaming_enum, idb_event::enum_renamed,
  idb_event::changing_enum_bf, idb_event::enum_bf_changed, idb_event::changing_enum_cmt, idb_event::enum_cmt_changed,
  idb_event::enum_member_created, idb_event::deleting_enum_member, idb_event::enum_member_deleted, idb_event::struc_created,
  idb_event::deleting_struc, idb_event::struc_deleted, idb_event::changing_struc_align, idb_event::struc_align_changed,
  idb_event::renaming_struc, idb_event::struc_renamed, idb_event::expanding_struc, idb_event::struc_expanded,
  idb_event::struc_member_created, idb_event::deleting_struc_member, idb_event::struc_member_deleted, idb_event::renaming_struc_member,
  idb_event::struc_member_renamed, idb_event::changing_struc_member, idb_event::struc_member_changed, idb_event::changing_struc_cmt,
  idb_event::struc_cmt_changed, idb_event::segm_added, idb_event::deleting_segm, idb_event::segm_deleted,
  idb_event::changing_segm_start, idb_event::segm_start_changed, idb_event::changing_segm_end, idb_event::segm_end_changed,
  idb_event::changing_segm_name, idb_event::segm_name_changed, idb_event::changing_segm_class, idb_event::segm_class_changed,
  idb_event::segm_attrs_updated, idb_event::segm_moved, idb_event::allsegs_moved, idb_event::func_added,
  idb_event::func_updated, idb_event::set_func_start, idb_event::set_func_end, idb_event::deleting_func,
  idb_event::frame_deleted, idb_event::thunk_func_created, idb_event::func_tail_appended, idb_event::deleting_func_tail,
  idb_event::func_tail_deleted, idb_event::tail_owner_changed, idb_event::func_noret_changed, idb_event::stkpnts_changed,
  idb_event::updating_tryblks, idb_event::tryblks_updated, idb_event::deleting_tryblks, idb_event::sgr_changed,
  idb_event::make_code, idb_event::make_data, idb_event::destroyed_items, idb_event::renamed,
  idb_event::byte_patched, idb_event::changing_cmt, idb_event::cmt_changed, idb_event::changing_range_cmt,
  idb_event::range_cmt_changed, idb_event::extra_cmt_changed
 IDB event codes. More...


idaman processor_t ida_export_data ph
 current processor
idaman asm_t ida_export_data ash
 current assembler

Macro Definition Documentation


The interface version number.

see also IDA_SDK_VERSION from pro.h

Enumeration Type Documentation

Flags passed as 'level' parameter to set_processor_type()


set processor type for old idb


set processor type for new idb; if the user has specified a compatible processor, return success without changing it.

if failure, call loader_failure()


the same as SETPROC_LOADER but non-fatal failures.


set user-specified processor used for -p and manual processor change at later time

Function Documentation

idaman int ida_export is_align_insn ( ea_t  ea)

If the instruction at 'ea' looks like an alignment instruction, return its length in bytes.

Otherwise return 0.

idaman ssize_t ida_export get_reg_name ( qstring buf,
int  reg,
size_t  width,
int  reghi = -1 

Get text representation of a register.

For most processors this function will just return processor_t::reg_names[reg]. If the processor module has implemented processor_t::get_reg_name, it will be used instead

bufoutput buffer
reginternal register number as defined in the processor module
widthregister width in bytes
reghiif specified, then this function will return the register pair
length of register name in bytes or -1 if failure
const char* get_reg_info ( const char *  regname,
bitrange_t bitrange 

Get register information - useful for registers like al, ah, dil, etc.

NULL no such register
idaman bool ida_export parse_reg_name ( reg_info_t ri,
const char *  regname 

Get register info by name.

regnamename of register
idaman bool ida_export set_processor_type ( const char *  procname,
setproc_level_t  level 

Set target processor type.

Once a processor module is loaded, it can not be replaced until we close the idb.

procnamename of processor type (one of names present in processor_t::psnames)
idaman char* ida_export get_idp_name ( char *  buf,
size_t  bufsize 

Get name of the current processor module.

The name is derived from the file name. For example, for IBM PC the module is named "pc.w32" (windows version), then the module name is "PC" (uppercase). If no processor module is loaded, this function will return NULL

bufthe output buffer, should be at least QMAXFILE length
bufsizesize of output buffer
idaman bool ida_export set_target_assembler ( int  asmnum)

Set target assembler.

asmnumnumber of assembler in the current processor module