Module ida_idp
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Module ida_idp

IDA Plugin SDK API wrapper: idp

Classes
  asm_t
Proxy of C++ asm_t class
  reg_info_t
Proxy of C++ reg_info_t class
  IDP_Hooks
Proxy of C++ IDP_Hooks class
  processor_t
Base class for all processor module scripts
  IDB_Hooks
Proxy of C++ IDB_Hooks class
Functions
PyObject *
AssembleLine(ea, cs, ip, use32, nonnul_line)
Assemble an instruction to a string (display a warning if an error is found)
bool
has_cf_chg(feature, opnum)
Does an instruction with the specified feature modify the i-th operand?
bool
has_cf_use(feature, opnum)
Does an instruction with the specified feature use a value of the i-th operand?
bool
has_insn_feature(icode, bit)
Does the specified instruction have the specified feature?
bool
is_call_insn(insn)
Is the instruction a "call"?
bool
is_ret_insn(insn, strict=True)
Is the instruction a "return"?
bool
is_indirect_jump_insn(insn)
Is the instruction an indirect jump?
bool
is_basic_block_end(insn, call_insn_stops_block)
Is the instruction the end of a basic block?
int
str2reg(p)
Get any reg number (-1 on error)
int
is_align_insn(ea)
If the instruction at 'ea' looks like an alignment instruction, return its length in bytes.
ssize_t
get_reg_name(reg, width, reghi=-1)
Get text representation of a register.
char const *
get_reg_info(regname, bitrange)
Get register information - useful for registers like al, ah, dil, etc.
int
compare(a, b)
compare(a, b) -> int compare(a, b) -> int compare(a, b) -> int
bool
parse_reg_name(ri, regname)
Get register info by name.
size_t
sizeof_ldbl()
Get size of long double.
bool
set_processor_type(procname, level)
Set target processor type.
char *
get_idp_name()
Get name of the current processor module.
bool
set_target_assembler(asmnum)
Set target assembler.
bool
delay_slot_insn(ea, bexec, fexec)
Helper function to get the delay slot instruction.
 
gen_idb_event(code)
the kernel will use this function to generate idb_events
char const *
cfg_get_cc_parm(compid, name)
char const *
cfg_get_cc_header_path(compid)
char const *
cfg_get_cc_predefined_macros(compid)
bool
assemble(ea, cs, ip, use32, line)
Assemble an instruction into the database (display a warning if an error is found)
size_t
ph_get_id()
Returns the 'ph.id' field
size_t
ph_get_version()
Returns the 'ph.version'
size_t
ph_get_flag()
Returns the 'ph.flag'
size_t
ph_get_cnbits()
Returns the 'ph.cnbits'
size_t
ph_get_dnbits()
Returns the 'ph.dnbits'
size_t
ph_get_reg_first_sreg()
Returns the 'ph.reg_first_sreg'
size_t
ph_get_reg_last_sreg()
Returns the 'ph.reg_last_sreg'
size_t
ph_get_segreg_size()
Returns the 'ph.segreg_size'
size_t
ph_get_reg_code_sreg()
Returns the 'ph.reg_code_sreg'
size_t
ph_get_reg_data_sreg()
Returns the 'ph.reg_data_sreg'
size_t
ph_get_icode_return()
Returns the 'ph.icode_return'
size_t
ph_get_instruc_start()
Returns the 'ph.instruc_start'
size_t
ph_get_instruc_end()
Returns the 'ph.instruc_end'
size_t
ph_get_tbyte_size()
Returns the 'ph.tbyte_size' field as defined in he processor module
PyObject *
ph_get_instruc()
Returns a list of tuples (instruction_name, instruction_feature) containing the instructions list as defined in he processor module
PyObject *
ph_get_regnames()
Returns the list of register names as defined in the processor module
PyObject *
ph_get_operand_info(ea, n)
Returns the operand information given an ea and operand number.
 
ph_calcrel(ea)
ssize_t
ph_find_reg_value(insn, reg)
ssize_t
ph_find_op_value(insn, op)
Variables
  IDP_INTERFACE_VERSION = 700
The interface version number.see also 'IDA_SDK_VERSION' from 'pro.h'
  AS_OFFST = 1
offsets are 'offset xxx' ?
  AS_COLON = 2
create colons after data names ?
  AS_UDATA = 4
can use '?' in data directives
  AS_2CHRE = 8
double char constants are: "xy
  AS_NCHRE = 16
char constants are: 'x
  AS_N2CHR = 32
can't have 2 byte char consts
  AS_1TEXT = 64
1 text per line, no bytes
  AS_NHIAS = 128
no characters with high bit
  AS_NCMAS = 256
no commas in ascii directives
  AS_HEXFM = 3584
mask - hex number format
  ASH_HEXF0 = 0
34h
  ASH_HEXF1 = 512
h'34
  ASH_HEXF2 = 1024
34
  ASH_HEXF3 = 1536
0x34
  ASH_HEXF4 = 2048
$34
  ASH_HEXF5 = 2560
<^R > (radix)
  AS_DECFM = 12288
mask - decimal number format
  ASD_DECF0 = 0
34
  ASD_DECF1 = 4096
#34
  ASD_DECF2 = 8192
  ASD_DECF3 = 12288
.34
  AS_OCTFM = 114688
mask - octal number format
  ASO_OCTF0 = 0
123o
  ASO_OCTF1 = 16384
0123
  ASO_OCTF2 = 32768
123
  ASO_OCTF3 = 49152
@123
  ASO_OCTF4 = 65536
o'123
  ASO_OCTF5 = 81920
123q
  ASO_OCTF6 = 98304
~123
  ASO_OCTF7 = 114688
q'123
  AS_BINFM = 917504
mask - binary number format
  ASB_BINF0 = 0
010101b
  ASB_BINF1 = 131072
^B010101
  ASB_BINF2 = 262144
%010101
  ASB_BINF3 = 393216
0b1010101
  ASB_BINF4 = 524288
b'1010101
  ASB_BINF5 = 655360
b'1010101'
  AS_UNEQU = 1048576
replace undefined data items with EQU (for ANTA's A80)
  AS_ONEDUP = 2097152
One array definition per line.
  AS_NOXRF = 4194304
Disable xrefs during the output file generation.
  AS_XTRNTYPE = 8388608
Assembler understands type of extern symbols as ":type" suffix.
  AS_RELSUP = 16777216
Checkarg: 'and','or','xor' operations with addresses are possible.
  AS_LALIGN = 33554432
Labels at "align" keyword are supported.
  AS_NOCODECLN = 67108864
don't create colons after code names
  AS_NOSPACE = 268435456
No spaces in expressions.
  AS_ALIGN2 = 536870912
(.align 5 means to align at 32byte boundary)
  AS_ASCIIC = 1073741824
( , and similar)
  AS_ASCIIZ = 2147483648
ascii directive inserts implicit zero byte at the end
  AS2_BRACE = 1
Use braces for all expressions.
  AS2_STRINV = 2
(For processors with bytes bigger than 8 bits)
  AS2_BYTE1CHAR = 4
Meaningful only for wide byte processors.
  AS2_IDEALDSCR = 8
Description of struc/union is in the 'reverse' form (keyword before name) the same as in borland tasm ideal
  AS2_TERSESTR = 16
NAME<fld,fld,...> is supported.
  AS2_COLONSUF = 32
addresses may have ":xx" suffix this suffix must be ignored when extracting the address under the cursor
  AS2_YWORD = 64
a_yword field is present and valid
  cvar = _ida_idp.cvar
  SETPROC_IDB = 0
  SETPROC_LOADER = 1
  SETPROC_LOADER_NON_FATAL = 2
  SETPROC_USER = 3
  closebase = 0
  savebase = 1
  upgraded = 2
  auto_empty = 3
  auto_empty_finally = 4
  determined_main = 5
  local_types_changed = 6
  extlang_changed = 7
  idasgn_loaded = 8
  kernel_config_loaded = 9
  loader_finished = 10
  flow_chart_created = 11
  compiler_changed = 12
  changing_ti = 13
  ti_changed = 14
  changing_op_ti = 15
  op_ti_changed = 16
  changing_op_type = 17
  op_type_changed = 18
  enum_created = 19
  deleting_enum = 20
  enum_deleted = 21
  renaming_enum = 22
  enum_renamed = 23
  changing_enum_bf = 24
  enum_bf_changed = 25
  changing_enum_cmt = 26
  enum_cmt_changed = 27
  enum_member_created = 28
  deleting_enum_member = 29
  enum_member_deleted = 30
  struc_created = 31
  deleting_struc = 32
  struc_deleted = 33
  changing_struc_align = 34
  struc_align_changed = 35
  renaming_struc = 36
  struc_renamed = 37
  expanding_struc = 38
  struc_expanded = 39
  struc_member_created = 40
  deleting_struc_member = 41
  struc_member_deleted = 42
  renaming_struc_member = 43
  struc_member_renamed = 44
  changing_struc_member = 45
  struc_member_changed = 46
  changing_struc_cmt = 47
  struc_cmt_changed = 48
  segm_added = 49
  deleting_segm = 50
  segm_deleted = 51
  changing_segm_start = 52
  segm_start_changed = 53
  changing_segm_end = 54
  segm_end_changed = 55
  changing_segm_name = 56
  segm_name_changed = 57
  changing_segm_class = 58
  segm_class_changed = 59
  segm_attrs_updated = 60
  segm_moved = 61
  allsegs_moved = 62
  func_added = 63
  func_updated = 64
  set_func_start = 65
  set_func_end = 66
  deleting_func = 67
  frame_deleted = 68
  thunk_func_created = 69
  func_tail_appended = 70
  deleting_func_tail = 71
  func_tail_deleted = 72
  tail_owner_changed = 73
  func_noret_changed = 74
  stkpnts_changed = 75
  updating_tryblks = 76
  tryblks_updated = 77
  deleting_tryblks = 78
  sgr_changed = 79
  make_code = 80
  make_data = 81
  destroyed_items = 82
  renamed = 83
  byte_patched = 84
  changing_cmt = 85
  cmt_changed = 86
  changing_range_cmt = 87
  range_cmt_changed = 88
  extra_cmt_changed = 89
  item_color_changed = 90
  callee_addr_changed = 91
  bookmark_changed = 92
  sgr_deleted = 93
  IDPOPT_CST = 6
  IDPOPT_PRI_DEFAULT = 1
  IDPOPT_PRI_HIGH = 2
  IDPOPT_NUM_INT = 0
  IDPOPT_NUM_CHAR = 16777216
  IDPOPT_NUM_SHORT = 33554432
  IDPOPT_NUM_RANGE = 67108864
  IDPOPT_NUM_UNS = 134217728
  IDPOPT_BIT_UINT = 0
  IDPOPT_BIT_UCHAR = 16777216
  IDPOPT_BIT_USHORT = 33554432
  IDPOPT_BIT_BOOL = 50331648
  IDPOPT_BIT_INVRES = 67108864
  IDPOPT_STR_QSTRING = 16777216
  IDPOPT_STR_LONG = 33554432
  IDPOPT_I64_RANGES = 16777216
  IDPOPT_I64_UNS = 33554432
  CUSTOM_INSN_ITYPE = 32768
Custom instruction codes defined by processor extension plugins must be greater than or equal to this
  REG_SPOIL = 2147483648
processor_t::use_regarg_type uses this bit in the return value to indicate that the register value has been spoiled
  REAL_ERROR_FORMAT = -1
  REAL_ERROR_RANGE = -2
  REAL_ERROR_BADDATA = -3
  OP_FP_BASED = 0
operand is FP based
  OP_SP_BASED = 1
operand is SP based
  OP_SP_ADD = 0
operand value is added to the pointer
  OP_SP_SUB = 2
operand value is subtracted from the pointer
  PLFM_386 = 0
Intel 80x86.
  PLFM_Z80 = 1
8085, Z80
  PLFM_I860 = 2
Intel 860.
  PLFM_8051 = 3
8051
  PLFM_TMS = 4
Texas Instruments TMS320C5x.
  PLFM_6502 = 5
6502
  PLFM_PDP = 6
PDP11.
  PLFM_68K = 7
Motorola 680x0.
  PLFM_JAVA = 8
Java.
  PLFM_6800 = 9
Motorola 68xx.
  PLFM_ST7 = 10
SGS-Thomson ST7.
  PLFM_MC6812 = 11
Motorola 68HC12.
  PLFM_MIPS = 12
MIPS.
  PLFM_ARM = 13
Advanced RISC Machines.
  PLFM_TMSC6 = 14
Texas Instruments TMS320C6x.
  PLFM_PPC = 15
PowerPC.
  PLFM_80196 = 16
Intel 80196.
  PLFM_Z8 = 17
Z8.
  PLFM_SH = 18
Renesas (formerly Hitachi) SuperH.
  PLFM_NET = 19
Microsoft Visual Studio.Net.
  PLFM_AVR = 20
Atmel 8-bit RISC processor(s)
  PLFM_H8 = 21
Hitachi H8/300, H8/2000.
  PLFM_PIC = 22
Microchip's PIC.
  PLFM_SPARC = 23
SPARC.
  PLFM_ALPHA = 24
DEC Alpha.
  PLFM_HPPA = 25
Hewlett-Packard PA-RISC.
  PLFM_H8500 = 26
Hitachi H8/500.
  PLFM_TRICORE = 27
Tasking Tricore.
  PLFM_DSP56K = 28
Motorola DSP5600x.
  PLFM_C166 = 29
Siemens C166 family.
  PLFM_ST20 = 30
SGS-Thomson ST20.
  PLFM_IA64 = 31
Intel Itanium IA64.
  PLFM_I960 = 32
Intel 960.
  PLFM_F2MC = 33
Fujistu F2MC-16.
  PLFM_TMS320C54 = 34
Texas Instruments TMS320C54xx.
  PLFM_TMS320C55 = 35
Texas Instruments TMS320C55xx.
  PLFM_TRIMEDIA = 36
Trimedia.
  PLFM_M32R = 37
Mitsubishi 32bit RISC.
  PLFM_NEC_78K0 = 38
NEC 78K0.
  PLFM_NEC_78K0S = 39
NEC 78K0S.
  PLFM_M740 = 40
Mitsubishi 8bit.
  PLFM_M7700 = 41
Mitsubishi 16bit.
  PLFM_ST9 = 42
ST9+.
  PLFM_FR = 43
Fujitsu FR Family.
  PLFM_MC6816 = 44
Motorola 68HC16.
  PLFM_M7900 = 45
Mitsubishi 7900.
  PLFM_TMS320C3 = 46
Texas Instruments TMS320C3.
  PLFM_KR1878 = 47
Angstrem KR1878.
  PLFM_AD218X = 48
Analog Devices ADSP 218X.
  PLFM_OAKDSP = 49
Atmel OAK DSP.
  PLFM_TLCS900 = 50
Toshiba TLCS-900.
  PLFM_C39 = 51
Rockwell C39.
  PLFM_CR16 = 52
NSC CR16.
  PLFM_MN102L00 = 53
Panasonic MN10200.
  PLFM_TMS320C1X = 54
Texas Instruments TMS320C1x.
  PLFM_NEC_V850X = 55
NEC V850 and V850ES/E1/E2.
  PLFM_SCR_ADPT = 56
Processor module adapter for processor modules written in scripting languages.
  PLFM_EBC = 57
EFI Bytecode.
  PLFM_MSP430 = 58
Texas Instruments MSP430.
  PLFM_SPU = 59
Cell Broadband Engine Synergistic Processor Unit.
  PLFM_DALVIK = 60
Android Dalvik Virtual Machine.
  PLFM_65C816 = 61
65802/65816
  PLFM_M16C = 62
Renesas M16C.
  PLFM_ARC = 63
Argonaut RISC Core.
  PLFM_UNSP = 64
SunPlus unSP.
  PLFM_TMS320C28 = 65
Texas Instruments TMS320C28x.
  PLFM_DSP96K = 66
Motorola DSP96000.
  PLFM_SPC700 = 67
Sony SPC700.
  PLFM_AD2106X = 68
Analog Devices ADSP 2106X.
  PLFM_PIC16 = 69
Microchip's 16-bit PIC.
  PR_SEGS = 1
has segment registers?
  PR_USE32 = 2
supports 32-bit addressing?
  PR_DEFSEG32 = 4
segments are 32-bit by default
  PR_RNAMESOK = 8
allow user register names for location names
  PR_ADJSEGS = 32
IDA may adjust segments' starting/ending addresses.
  PR_DEFNUM = 192
mask - default number representation
  PRN_HEX = 0
hex
  PRN_OCT = 64
octal
  PRN_DEC = 128
decimal
  PRN_BIN = 192
binary
  PR_WORD_INS = 256
instruction codes are grouped 2bytes in binary line prefix
  PR_NOCHANGE = 512
(display only)
  PR_ASSEMBLE = 1024
Module has a built-in assembler and will react to ev_assemble.
  PR_ALIGN = 2048
All data items should be aligned properly.
  PR_TYPEINFO = 4096
ALL OF THEM SHOULD BE IMPLEMENTED!
  PR_USE64 = 8192
supports 64-bit addressing?
  PR_SGROTHER = 16384
the segment registers don't contain the segment selectors.
  PR_STACK_UP = 32768
the stack grows up
  PR_BINMEM = 65536
the processor module provides correct segmentation for binary files (i.e.
  PR_SEGTRANS = 131072
the processor module supports the segment translation feature (meaning it calculates the code addresses using the 'map_code_ea()' function)
  PR_CHK_XREF = 262144
don't allow near xrefs between segments with different bases
  PR_NO_SEGMOVE = 524288
(i.e.
  PR_USE_ARG_TYPES = 2097152
use {use_arg_types} callback
  PR_SCALE_STKVARS = 4194304
use {get_stkvar_scale} callback
  PR_DELAYED = 8388608
has delayed jumps and calls if this flag is set, {is_basic_block_end}, {has_delay_slot} should be implemented
  PR_ALIGN_INSN = 16777216
allow ida to create alignment instructions arbitrarily.
  PR_PURGING = 33554432
there are calling conventions which may purge bytes from the stack
  PR_CNDINSNS = 67108864
has conditional instructions
  PR_USE_TBYTE = 134217728
'BTMT_SPECFLT' means _TBYTE type
  PR_DEFSEG64 = 268435456
segments are 64-bit by default
  CF_STOP = 1
next instruction
  CF_CALL = 2
CALL instruction (should make a procedure here)
  CF_CHG1 = 4
The instruction modifies the first operand.
  CF_CHG2 = 8
The instruction modifies the second operand.
  CF_CHG3 = 16
The instruction modifies the third operand.
  CF_CHG4 = 32
The instruction modifies 4 operand.
  CF_CHG5 = 64
The instruction modifies 5 operand.
  CF_CHG6 = 128
The instruction modifies 6 operand.
  CF_USE1 = 256
The instruction uses value of the first operand.
  CF_USE2 = 512
The instruction uses value of the second operand.
  CF_USE3 = 1024
The instruction uses value of the third operand.
  CF_USE4 = 2048
The instruction uses value of the 4 operand.
  CF_USE5 = 4096
The instruction uses value of the 5 operand.
  CF_USE6 = 8192
The instruction uses value of the 6 operand.
  CF_JUMP = 16384
jump or call (thus needs additional analysis)
  CF_SHFT = 32768
Bit-shift instruction (shl,shr...)
  CF_HLL = 65536
language function.
  IDPOPT_STR = 1
  IDPOPT_NUM = 2
  IDPOPT_BIT = 3
  IDPOPT_FLT = 4
  IDPOPT_I64 = 5
  IDPOPT_OK = 0
  IDPOPT_BADKEY = 1
  IDPOPT_BADTYPE = 2
  IDPOPT_BADVALUE = 3
  ph = <ida_idp.__ph object>
  __package__ = None
Function Details

AssembleLine(ea, cs, ip, use32, nonnul_line)

 

Assemble an instruction to a string (display a warning if an error is found)

Parameters:
  • ea - linear address of instruction
  • cs - cs of instruction
  • ip - ip of instruction
  • use32 - is 32bit segment
  • line - line to assemble
Returns: PyObject *
  • None on failure
  • or a string containing the assembled instruction

has_cf_chg(feature, opnum)

 

Does an instruction with the specified feature modify the i-th operand?

Parameters:
  • feature, (C++ - uint32)
  • opnum, (C++ - uint)
Returns: bool

has_cf_use(feature, opnum)

 

Does an instruction with the specified feature use a value of the i-th operand?

Parameters:
  • feature, (C++ - uint32)
  • opnum, (C++ - uint)
Returns: bool

has_insn_feature(icode, bit)

 

Does the specified instruction have the specified feature?

Parameters:
  • icode, (C++ - int)
  • bit, (C++ - uint32)
Returns: bool

is_call_insn(insn)

 

Is the instruction a "call"?

Parameters:
  • insn, (C++ - const insn_t &)
Returns: bool

is_ret_insn(insn, strict=True)

 

Is the instruction a "return"?

Parameters:
  • insn, (C++ - const insn_t &)
  • strict, (C++ - bool)
Returns: bool

is_indirect_jump_insn(insn)

 

Is the instruction an indirect jump?

Parameters:
  • insn, (C++ - const insn_t &)
Returns: bool

is_basic_block_end(insn, call_insn_stops_block)

 

Is the instruction the end of a basic block?

Parameters:
  • insn, (C++ - const insn_t &)
  • call_insn_stops_block, (C++ - bool)
Returns: bool

str2reg(p)

 

Get any reg number (-1 on error)

Parameters:
  • p, (C++ - const char *)
Returns: int

is_align_insn(ea)

 

If the instruction at 'ea' looks like an alignment instruction, return its length in bytes. Otherwise return 0.

Parameters:
  • ea, (C++ - ea_t)
Returns: int

get_reg_name(reg, width, reghi=-1)

 

Get text representation of a register. For most processors this function will just return {reg_names}[reg]. If the processor module has implemented processor_t::get_reg_name, it will be used instead

Parameters:
  • reg - internal register number as defined in the processor module (C++: int)
  • width - register width in bytes (C++: size_t)
  • reghi - if specified, then this function will return the register pair (C++: int)
Returns: ssize_t
length of register name in bytes or -1 if failure

get_reg_info(regname, bitrange)

 

Get register information - useful for registers like al, ah, dil, etc.

Parameters:
  • regname, (C++ - const char *)
  • bitrange, (C++ - bitrange_t *)
Returns: char const *
NULL no such register

parse_reg_name(ri, regname)

 

Get register info by name.

Parameters:
  • ri - result (C++: reg_info_t *)
  • regname - name of register (C++: const char *)
Returns: bool
success

set_processor_type(procname, level)

 

Set target processor type. Once a processor module is loaded, it can not be replaced until we close the idb.

Parameters:
  • procname - name of processor type (one of names present in {psnames}) (C++: const char *)
  • level - SETPROC_ (C++: setproc_level_t)
Returns: bool
success

get_idp_name()

 

Get name of the current processor module. The name is derived from the file name. For example, for IBM PC the module is named "pc.w32" (windows version), then the module name is "PC" (uppercase). If no processor module is loaded, this function will return NULL

Returns: char *

set_target_assembler(asmnum)

 

Set target assembler.

Parameters:
  • asmnum - number of assembler in the current processor module (C++: int)
Returns: bool
success

delay_slot_insn(ea, bexec, fexec)

 

Helper function to get the delay slot instruction.

Parameters:
  • ea, (C++ - ea_t *)
  • bexec, (C++ - bool *)
  • fexec, (C++ - bool *)
Returns: bool

gen_idb_event(code)

 

the kernel will use this function to generate idb_events

Parameters:
  • code, (C++ - idb_event::event_code_t)

assemble(ea, cs, ip, use32, line)

 

Assemble an instruction into the database (display a warning if an error is found)

Parameters:
  • ea - linear address of instruction
  • cs - cs of instruction
  • ip - ip of instruction
  • use32 - is 32bit segment?
  • line - line to assemble
Returns: bool
Boolean. True on success.

ph_get_operand_info(ea, n)

 

Returns the operand information given an ea and operand number.

Parameters:
  • ea - address
  • n - operand number
Returns: PyObject *
Returns an idd_opinfo_t as a tuple: (modified, ea, reg_ival, regidx, value_size). Please refer to idd_opinfo_t structure in the SDK.

Variables Details

AS_ALIGN2

(.align 5 means to align at 32byte boundary)

.align directive expects an exponent rather than a power of 2

Value:
536870912

AS_ASCIIC

( , and similar)

ascii directive accepts C-like escape sequences

Value:
1073741824

AS2_STRINV

(For processors with bytes bigger than 8 bits)

Invert meaning of {wide_high_byte_first} for text strings

Value:
2

AS2_BYTE1CHAR

Meaningful only for wide byte processors.

One symbol per processor byte

Value:
4

AS2_TERSESTR

NAME<fld,fld,...> is supported.

'terse' structure initialization form

Value:
16

PR_NOCHANGE

(display only)

The user can't change segments and code/data attributes

Value:
512

PR_TYPEINFO

ALL OF THEM SHOULD BE IMPLEMENTED!

the processor module supports type information callbacks

Value:
4096

PR_BINMEM

the processor module provides correct segmentation for binary files (i.e. it creates additional segments) The kernel will not ask the user to specify the RAM/ROM sizes

Value:
65536

PR_NO_SEGMOVE

(i.e. the user can't move segments)

the processor module doesn't support 'move_segm()'

Value:
524288

PR_ALIGN_INSN

allow ida to create alignment instructions arbitrarily. Since these instructions might lead to other wrong instructions and spoil the listing, IDA does not create them by default anymore

Value:
16777216

CF_STOP

next instruction

Instruction doesn't pass execution to the

Value:
1

CF_JUMP

jump or call (thus needs additional analysis)

The instruction passes execution using indirect

Value:
16384

CF_HLL

language function.

Instruction may be present in a high level

Value:
65536