IDA supports ARM/Thumb Macro Assembler as a target assembler. However, some number formats are not supported by the kernel and will not be accepted by the assembler utility.
To decode Aarch64 (ARM64) instructions the segment must be declared as 64-bit.
If this option is on, IDA will simplify instructions and replace them by clearer pseudo-instructions For example,
MOV PC, LR
is replaced by
RETDisable pointer dereferencing
If this option is on, IDA will not use =label syntax for pointer references. For example,
LDR R1, =dst ... off_0_1003C DCD dst
will be replaced by
LDR R1, off_0_1003CEnable macros
If this option is on, IDA will use macro instructions to simplify disassembly For example,
MOV R7,#2 ADD R7,R7,#3
will be replaced by
MOV R7, #5
Apart from the ADD instruction, SUB, ORR, LSL instructions are supported
Also: MVN Rx, #x => MOV Rx, #~xNo automatic ARM-Thumb switch
If this option is on, IDA will not propagate ARM-Thumb modes automatically when following jumps and calls.Disable BL jumps detection
Some ARM compilers in Thumb mode use BL (branch-and-link) instead of B (branch) for long jumps, since BL has more range. By default, IDA tries to determine if BL is a jump or a call. You can override IDA's decision using commands in Edit/Other menu (Force BL call/Force BL jump). If your target does not use this trick, you can set this option and IDA will always treat BL as a call.Edit ARM architecture options
This button allows you to edit various features of the ARM architecture. This will affect the disassembly of some instructions depending on whether the selected architecture supports them. For details, see the ARM Architecture Reference Manual.
You can configure the architecture options from the command line. For that, use the -parm:<option1[;option2...]> switch. The following options are accepted:
ARMv<N> - base ARM architecture version (e.g. ARMv4, ARMv4T, ARMv5TE, ..., ARMv7-M, ARMv7-A) or
<name> - ARM core name (e.g. ARM7TDMI, ARM926EJ-S, PXA270, Cortex-M3, Cortex-A8)
Additionally, a special name "armmeta" can be used to enable decoding of all known instructions.
The options above will set some default values that can be adjusted further:
NoVFP/VFPv<N> - disable or enable support for VFP instructions (e.g. VFPv3). NoNEON/NEON/NEON-FMA - disable or enable support for NEON (aka Advanced SIMD) instructions. NoThumb/Thumb/Thumb-2 - disable or enable support for Thumb (16-bit) or Thumb-2 (16/32-bit) instructions. NoARM/ARM - disable or enable support for ARM instructions. XScale - support for XScale-specific instructions. Implies ARMv5TE. NoWMMX/WMMXv1/WMMXv2 - support for Intel Wireless MMX extensions (v1 or v2). Implies XScale.See
Change segment register value Set default segment register valuecommands to learn how to specify the segment register value.