IDA Disassemblies Gallery

Intel IA-64 (Itanium)

Assembler code
.text:0000000000421100 .text:0000000000421100 // =============== S U B R O U T I N E ======================================= .text:0000000000421100 .text:0000000000421100 .text:0000000000421100 sub_421100: // CODE XREF: sub_41FF40+3C↑p .text:0000000000421100 alloc r37 = ar.pfs, 0, 9, 2, 0 .text:0000000000421106 mov r39 = pr .text:000000000042110C adds sp = -32, sp .text:0000000000421110 or r40 = gp, r0;; .text:0000000000421116 cmp4.eq p14, p15 = 2, r32 .text:000000000042111C mov r36 = b0;; .text:0000000000421120 ld8.nta r3 = [sp] .text:0000000000421126 mov.i r38 = ar.lc // loop count register .text:000000000042112C (p14) br.cond.dpnt.few loc_4211D0;; .text:0000000000421130 cmp4.eq p14, p15 = 1, r0 .text:0000000000421136 cmp4.eq p13, p0 = 15, r32 .text:000000000042113C cmp4.eq p12, p0 = 21, r32;; .text:0000000000421140 cmp4.eq.or.andcm p14, p15 = 4, r32 .text:0000000000421146 cmp4.eq.or.andcm p14, p15 = 8, r32 .text:000000000042114C cmp4.eq.or.andcm p14, p15 = 11, r32 .text:0000000000421150 (p14) br.cond.dpnt.few loc_4211B0 .text:0000000000421156 (p13) br.cond.dpnt.few loc_4211A0 .text:000000000042115C (p12) br.cond.dpnt.few loc_421190;; .text:0000000000421160 cmp4.eq p14, p15 = 22, r32 .text:0000000000421166 nop.f 0 .text:000000000042116C (p14) br.cond.dpnt.few loc_421180;; .text:0000000000421170 mov r8 = -1 .text:0000000000421176 nop.f 0 .text:000000000042117C br.few loc_421430;; .text:0000000000421180 // --------------------------------------------------------------------------- .text:0000000000421180 .text:0000000000421180 loc_421180: // CODE XREF: sub_421100+6C↑j .text:0000000000421180 addl r28 = -2086752, gp // unk_4308A0 .text:0000000000421186 nop.f 0 .text:000000000042118C br.few loc_4211E0;;
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